Parliament Replies Detail Design-Linked Incentive Scale as Semicon 2.0 Takes Shape

Two Lok Sabha replies from February 2026 set out how the government frames its semiconductor design strategy, describing it as an effort to build a self-reliant chip design ecosystem around the country's talent pool, global design leadership and a growing startup base. The Design Linked Incentive Scheme sits within the Semicon India Program launched in 2022, which the replies place inside the broader Make in India and Atmanirbhar Bharat strategy covering assembly, components, chip design, fabrication and packaging. ^{[1] [1] [2]}

On performance, the replies state that 24 chip and system-on-chip design projects worth a total project value of Rs 900 crore have been approved, including design infrastructure investment. They report 100 fabless chip design companies supported with access to advanced design infrastructure, cumulatively using 55 lakh hours of tools; 16 designs taped out; and fabricated chips produced across multiple foundries including a 12-nanometre node at TSMC. The fabricated tally differs across documents: one reply says 7 chips were fabricated, while a PIB backgrounder says startups completed 16 tape-outs with six chips fabricated at advanced foundry nodes. The documents also cite 10 patents filed, more than 140 reusable semiconductor IP cores developed, and 13 companies that raised venture capital. ^{[1] [1] [1] [3] [2]}

The workforce and training figures also diverge between documents. One Lok Sabha reply says advanced EDA tools were provided to 315 academic institutions, with projects initiated at 100 institutions, over 1 lakh engineering students enrolled in training and about 67,000 trained in chip design; it records 1.6 crore hours of EDA tool use by students and 122 chip designs submitted by 46 institutions for fabrication at the SCL foundry, of which 56 student-designed chips were fabricated, packaged and delivered back. A PIB backgrounder instead cites access to EDA tools across 397 universities and startups, with around 67,000 students and over 1,000 startup engineers using them, and places 122 academia tape-outs with 56 chips fabricated at 180 nm. ^{[1] [1] [3] [3]}

For the next phase, the PIB backgrounder states that a Rs 1,000-crore provision has been made for India Semiconductor Mission 2.0 in FY 2026-27, focused on producing semiconductor equipment and materials in India, designing full-stack Indian semiconductor intellectual property, and industry-led research and training centres. It projects a Rs 1,000-crore Design Linked Incentive outlay for 2026-27 supporting 30 design companies, 10 semiconductor IP cores and 200 design engineers, and says the programme is set to scale with a target of at least 50 fabless semiconductor companies in the next phase. Those are planned outcomes, not completed results. ^{[3] [3] [3] [3]}

What Semicon 2.0 changes in practice remains partly unresolved in the captured material. A Lok Sabha question on the second phase of the Design-Linked Incentive scheme asks whether the government is aware of differences between policymakers and industry over DLI 2.0's structure, whether a proposed pari-passu funding model would affect startups and chip design companies in Maharashtra, and whether matching private capital could disadvantage smaller firms and early-stage innovators. The ministerial answer does not address those specifics, restating the overall semiconductor strategy and listing DLI performance figures instead. The disbursing authority, eligibility rules and funding terms for design startups under the next phase are not set out in the captured passages. ^{[1] [1] [1]}